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ics for consumer electronics vps-decoder sda 5642-6/x data sheet 02.97
edition 02.97 this edition was realized using the software system framemaker a . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1997. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered. sda 5642-6/x revision history: current version: 02.97 previous version: page (in previous version) page (in current version) subjects (major changes since last revision)
sda 5642-6/x table of contents page semiconductor group 3 02.97 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.1 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.2 chip address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.4 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 order of data output on the i 2 c bus and bit allocation . . . . . . . . . . . . . . . 12 2.4 description of davn and ehb outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 vps-receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 control register write ( i 2 c-bus write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 data register read ( i 2 c-bus read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 davn and ehb timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4 position of vps data lines within the vertical blanking interval . . . . . . . . . 23 5.5 definition of voltage levels for vps data line . . . . . . . . . . . . . . . . . . . . . . 23 5.6 data format of programme delivery data in the dedicated tv line (vps) 24 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 purchase of siemens i 2 c components conveys the license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips.
p-dip-14-1 p-dso-20-1 vps-decoder sda 5642-6/x semiconductor group 4 02.97 mos type ordering code package sda 5642-6 q67100-h5182 p-dip-14-1 sda 5642-6x q67106-h5183 p-dso-20-1 (smd) 1 general description the sda 5642-6 vps decoder chip receives all vps data. 1.1 features ? on chip data slicer ? low external component count ? i 2 c-bus interface communication with external microcontroller ? 5 v supply voltage ? video input signal level: 0.7 vpp to 2.0 vpp ? technology: cmos ? p-dip-14-1 and p-dso-20-1 package
sda 5642-6/x semiconductor group 5 02.97 1.2 pin configurations figure 1 p-dip-14-1 p-dso-20-1
sda 5642-6/x semiconductor group 6 02.97 1.3 pin description pin no. symbol function p-dip-14-1 p-dso-20-1 1 v ss ground (0 v) 1 v ssa analog ground (0 v) 2 v ssd digital ground (0 v) 3, 8, 13, 18 n.c. not connected 2 4 scl serial clock input of i 2 c bus. 3 5 sda serial data input of i 2 c bus. 4 6 cs0 chip select input determining the i 2 c-bus addresses: 20 h / 21 h , when pulled low 22 h / 23 h , when pulled high. 5 7 vcs video composite sync output from sync slicer used for pll based clock generation. 6 9 davn data available output active low, when vps data is received. 7 10 ehb output signaling the presence of the first field active high. 8 11 ti test input; activates test mode when pulled high. connect to ground for operating mode. 9 12 pd1 phase detector/charge pump output of data pll (dapll). 10 14 pd2/ vco2 connector of the loop filter for the syspll. 11 15 vco1 input to the voltage controlled oscillator #1 of the dapll. 12 16 i ref reference current input for the on-chip analog circuit. 13 17 cvbs composite video signal input. 14 v dd positive supply voltage (+ 5 v nom.). 19 v ddd positive supply voltage for the digital circuits (+ 5 v nom.). 20 v dda positive supply voltage for the analog circuits (+ 5 v nom.).
sda 5642-6/x semiconductor group 7 02.97 1.4 block diagram figure 2
sda 5642-6/x semiconductor group 8 02.97 2 system description 2.1 functions referring to the functional block diagram of the vps decoder, the composite video signal with negative going sync pulses is coupled to the pin cvbs through a capacitor which is used for clamping the bottom of the sync pulses to an internally fixed level. the signal is passed on to the slicer, an analogue circuitry separating the sync and the data parts of the cvbs signal, thus yielding the digital composite sync signal vcs and a digital data signal for further processing by comparing those signals to internally generated slicing levels. the output of the sync separator is forwarded, on one hand, to the output pin vcs, and on the other hand, to the clock generator and the timing block. the vcs signal represents a key signal that is used for deriving a system clock signal by means of a pll and all other timing signal. the data slicer separates the data signal from the cvbs signal by comparing the video voltage to an internally generated slicing level which is found by averaging the data signal during tv line no. 16. the clock generator delivers the system clock needed for the basic timing as well as for the regeneraton of the dataclock. it is based on two phase locked loops (plls) all parts of which are integrated on chip with the exception of the loop filter components. each of the plls is composed of a voltage controlled relaxation oscillator (vco), a phase/ frequency detector (pfd), and a charge pump which converts the digital output signals of the pfd to an analogue current. that current is transformed to a control voltage for the vco by the off-chip loop filter. the generated vco frequency is 10 mhz. all signals necessary for the control of sync and data slicing as well as for the data acquisition are generated by the timing block. the extracted data bits of tv line no. 16 are checked for biphase errors. with no biphase errors encountered, the acquired bytes are stored in the transfer register to the i 2 c bus. that transfer is signalled by a h/l transition of the davn output. data are updated when a new data line has been received, provided that the chip is not accessed via the i 2 c bus at the same time. a micro controller can read the stored bytes via the i 2 c-bus interface at any time. however, one must be aware that the storage of new data from the acquisition interface is inhibited as long as the vps decoder is being accessed via the i 2 c bus.
sda 5642-6/x semiconductor group 9 02.97 2.2 i 2 c bus 2.2.1 general information the i 2 c-bus interface implemented on the vps decoder is a slave transmitter/receiver, i.e., both reading from and writing to the vps decoder is possible. the clock line scl is controlled only by the bus master usually being a micro controller, whereas the sda line is controlled either by the master or by the slave. a data transfer can only be initiated by the bus master when the bus is free, i.e., both sda and scl lines are in a high state. as a general rule for the i 2 c bus, the sda line changes state only when the scl line is low. the only exception to that rule are the start condition and the stop condition. further details are given below. the following abbreviations are used: start: start condition generated by master as: acknowledge by slave am: acknowledge by master nam: no acknowledge by master stop: stop condition generated by master 2.2.2 chip address there are two pairs of chip addresses, which are selected by the cs0-input pin according to the following table: cs0 input write mode read mode low 20 (hex) 21 (hex) high 22 (hex) 23 (hex)
sda 5642-6/x semiconductor group 10 02.97 2.2.3 write mode for writing to the vps decoder, the following format has to be used: description of data transfer (write mode) step1: in order to start a data transfer the master generates a start condition on the bus by pulling the sda line low while the scl line is held high. step 2: the bus master puts the chip address on the sda line during the next eight scl pulses. step 3: the master releases the sda line during the ninth clock pulse. thus the slave can generate an acknowledge (as) by pulling the sda line to a low level. step 4: the controller transmits the data byte to set the control register step 5: the slave acknowledges the reception of the byte. step 6: the master concludes the data communication by generating a stop condition. the write mode is used to set the i 2 c-bus control register which determines the operating mode: control register: default: all bits are set to 0 on power-up. the bits t4 through t7 are used for test purposes and must not be changed for normal operation by user software! (0 = normal operation) you may write 00 h , 01 h , 02 h , 03 h , 04 h , 05 h , 06 h , 07 h , 08 h , 09 h , 0a h , 0b h , 0c h , 0d h , 0e h , 0f h to the register without efect. this enables the sda 5642-6 to be used for vps decoding instead of the sda 5050 or sda 5649 without software problems. start chipaddress and write mode as byte to set control register as stop bit number: 76543210 t7 t6 t5 t4 t3 t2 t1 t0
sda 5642-6/x semiconductor group 11 02.97 2.2.4 read mode for reading from the vps decoder, the following format has to be used : the contents of up to 16 registers (bytes) can be read starting with byte 1 bit 7 (refer to the table order of data output on the i 2 c bus and... ) depending on the selected operating mode. description of data transfer (read mode) step1: to start a data transfer the master generates a start condition on the bus by pulling the sda line low while the scl line is held high. the byte address counter in the decoder is reset and points to the first byte to be output. step 2: the bus master puts the chip address on the sda line during the next eight scl pulses. step 3: the master releases the sda line during the ninth clock pulse. thus the slave can generate an acknowledge (as) by pulling the sda line to a low level. at this moment, the slave switches to transmitting mode. step 4: during the next eight clock pulses the slave puts the addressed data byte onto the sda line. step 5: the reception of the byte is acknowledged by the master device which, in turn, pulls down the sda line during the next scl clock pulse. by acknowledging a byte, the master prompts the slave to increment its internal address counter and to provide the output of the next data byte. step 6: steps no. 4 and no. 5 are repeated, until the desired amount of bytes have been read. step 7: the last byte is output by the slave since it will not be acknowledged by the master. step 8: to conclude the read operation, the master doesnt acknowledge the last byte to be received. a no acknowledge by the master (nam) causes the slave to switch from transmitting to receiving mode. note that the master can prematurely cease any reading operation by not acknowledging a byte. step 9: the master gains control over the sda line and concludes the data transfer by generating a stop condition on the bus, i. e., by producing a low/high transition on the sda line while the scl line is in a high state. with the sda and the scl lines being both in a high state, the i 2 c bus is free and ready for another data transfer to be started. start chipaddress read mode as 1st byte am ..... last byte nam stop
sda 5642-6/x semiconductor group 12 02.97 2.3 order of data output on the i 2 c bus and bit allocation i 2 c bus vps mode byte 1 bit 7 6 5 4 3 2 1 0 byte 11 bit 0 1) 1 2 3 4 5 6 7 byte 2 bit 7 6 5 4 3 2 1 0 byte 12 bit 0 1 2 3 4 5 6 7 byte 3 bit 7 6 5 4 3 2 1 0 byte 13 bit 0 1 2 3 4 5 6 7 byte 4 bit 7 6 5 4 3 2 1 0 byte 14 bit 0 1 2 3 4 5 6 7 1) transmission bit number t
sda 5642-6/x semiconductor group 13 02.97 1) transmission bit number byte 5 bit 7 6 5 4 3 2 1 0 byte 5 bit 0 1 2 3 4 5 6 7 byte 6 bit 7 6 5 4 3 2 1 0 byte 15 bit 0 1 2 3 4 5 6 7 byte 7 bit 7 6 5 4 3 2 1 0 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1 C set to 1 2.3 order of data output on the i 2 c bus and bit allocation (contd) i 2 c bus vps mode
sda 5642-6/x semiconductor group 14 02.97 2.4 description of davn and ehb outputs davn (data valid active low) ehb (first field active high) in test mode (i.e. ti = high), both davn and ehb are controlled by the cs0 pin and reproduce the state of the cs0 input. signal output vps mode davn h/l-transition (set low) in line 16 when valid vps data is received l/h-transition (set high) at the start of line 16 always set high on power-up or during i 2 c-bus accesses when the bus master doesnt acknowledge in order to generate the stop condition ehb l/h-transition at the beginning of the first field h/l-transition at the beginning of the second field
sda 5642-6/x semiconductor group 15 02.97 3 electrical characteristics absolute maximum ratings t a = 25 c parameter symbol limit values unit test condition min. typ. max. ambient temperature t a 070 c in operation storage temperature t stg C 40 125 c by storage total power dissipation p tot 300 mw power dissipation per output p dq 10 mw input voltage v im C 0.3 6 v supply voltage v dd C 0.3 6 v thermal resistance r th su 80 k/w note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. operating range supply voltage v dd 4.5 5 5.5 v supply current i dd 515ma ambient temperature range t a 070 c note: in the operating range the functions given in the circuit description are fulfilled.
sda 5642-6/x semiconductor group 16 02.97 electrical characteristics t a = 25 c parameter symbol limit values unit test condition min. typ. max. input signals sda, scl, cs0 h-input voltage v ih 0.7 v dd v dd v l-input voltage v il 0 0.3 v dd v input capacitance c i 10 pf input current i im 10 m a input signal ti h-input voltage v ih 0.9 v dd v dd v l-input voltage v il 0 0.1 v dd v input capacitance c i 10 pf input current i im 10 m a input signals cvbs (pos. video, neg. sync) video input signal level v cvbs 0.7 1.0 2.0 v 2 vpp with 0.8 v v sync and 1.2 v v dat synchron signal amplitude v sync 0.15 0.3 0.8 (1.0) v 1.0 v only related to vcs signal generation data amplitude v dat 0.25 1.5 v sync 0.5 1.2 v coupling capacitor c c 33 nf h-input current i ih 10 m a v i =5v l-input current i il C 1000 C 400 C 100 m a v i =0v source impedance r s 250 w leakage resistance at coupling capacitor r c 0.91 1 1.2 m w
sda 5642-6/x semiconductor group 17 02.97 output signals davn, ehb, vcs h-output voltage v qh v dd C 0.5 v i q = C 100 m a l-output voltage v ql 0.4 v i q = 1.6 ma output signals sda (open-drain-stage) l-output voltage v ql 0.4 v i q = 3.0 ma permissible output voltage 5.5 v pll-loop filter components (see application circuit) resistance at pd2/ vco2 r 1 6.8 k w resistance at vco1 r 2 1200 k w attenuation resistance r 3 6.8 k w resistance at pd2/ vco2 r 5 1200 k w integration capacitor c 1 2.2 nf integration capacitor c 3 33 nf vco C frequence range adjustment resistance at iref (for bias current adjustment) r 4 100 k w note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. electrical characteristics (contd) t a = 25 c parameter symbol limit values unit test condition min. typ. max.
sda 5642-6/x semiconductor group 18 02.97 figure 3 i 2 c-bus timing all values referred to v ih and v il levels. parameter symbol limit values unit min. max. clock frequency f scl 0 100 khz inactive time prior to new transmission start-up t buf 4.7 m s hold time during start condition t hd; sta 4.0 m s low-period of clock t low 4.7 m s high-period of clock t high 4.0 m s set-up time for data t su;dat 250 ns rise time for sda and scl signal t tlh 1 m s fall time for sda and scl signal t thl 300 ns set-up time for scl clock during stop condition t su; sto 4.7 m s
sda 5642-6/x semiconductor group 19 02.97 4 vps-receiver figure 4
sda 5642-6/x semiconductor group 20 02.97 5 appendix 5.1 control register write ( i 2 c-bus write) figure 5
sda 5642-6/x semiconductor group 21 02.97 5.2 data register read ( i 2 c-bus read) figure 6
sda 5642-6/x semiconductor group 22 02.97 5.3 davn and ehb timing figure 7
sda 5642-6/x semiconductor group 23 02.97 5.4 position of vps data lines within the vertical blanking interval figure 8 1) (shown for first field) 5.5 definition of voltage levels for vps data line figure 9
sda 5642-6/x semiconductor group 24 02.97 5.6 data format of programme delivery data in the dedicated tv line (vps) figure 10
sda 5642-6/x semiconductor group 25 02.97 figure 11
sda 5642-6/x semiconductor group 26 02.97 6 package outlines p-dip-14-1 (plastic dual in-line package) gpd05005 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm
sda 5642-6/x semiconductor group 27 02.97 p-dso-20-1 (plastic dual small outline package) gps05094 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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